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ISL5217EVAL1 Evaluation Kit User’s Manual
PRELIMINARY
Introduction
Application Note
Features
June 2001
AN9910.1
[ /Title
(AN99
10)
/Subjec
The ISL5217EVAL1 is an evaluation kit for the ISL5217
Quad Programmable Upconverter. The kit consists of an
evaluation Circuit Card Assembly (CCA) complete with the
ISL5217 device and additional circuitry to provide for control
via a computer parallel port. Windows based demonstration
software is provided for full user programmability and control
of all ISL5217 operational modes. The evaluation board
provides digital outputs which are accessible through
standard logic analyzer headers. It also provides both single
? Evaluation CCA complete with ISL5217 Programmable
Upconverter
? Windows-Based Demonstration Software
? Example Files For Common Modulation Techniques
? Parallel Port Ribbon Cable and Power Supply Cable
Reference Documents
? ISL5217EVAL1 CCA Demonstration Software in File
t
(ISL52
17EVA
L1
Evalua
tion
Kit
ended and differential analog outputs via SMA connectors
and Low Voltage Differential Signals (LVDS) outputs.
Documentation includes a user ’s manual, full evaluation
board schematics and PCB layout materials. Special filter
files, pattern files and example configuration script files are
included for quickly configuring the board.
Block Diagram
ISL5217.exe
? Example Configuration Files in *.js, Filter Files in *.coe,
and Pattern Files in *.pat
? ISL5217EVAL1 Schematics in File sch217eval1.pdf
? ISL5217EVAL1 Layout in File fab217eval1.pdf
User ’s
Manua
l)
/Autho
COMPUTER PARALLEL PORT
J10-COMP. INTFC
/17
J9-JTAG/MISC
J5-P<15:0>
SYNCO
J2 QIN<19:0>
J1 IIN<19:0>
CAS-IN-CLK
IIN<19:0> QIN<19:0>
r ()
/Keyw
ords
(Intersi
l
Corpor
ation,
semico
nducto
r, ,
Progra
U4
LVX161284
IEEE XCVR
/17
U10
XC9572XL
CPLD
/4
U5
HC244
BUFFER
/11
U3
XCV150-4PQ240C
FPGA
DATA /32
CONTROL /4
ADDRESS /20
DATA /16
ADDRESS /7
CONTROL /9
SERIAL CHANNEL A /5
SERIAL CHANNEL B /5
SERIAL CHANNEL C /5
SERIAL CHANNEL D /5
U2
CY7C1339
SRAM
U1
ISL5217
PROG. UP CONVERTER
P<15:0>
A<6:0>
RDMODE, OFFBIN, OUTEN<1:0>, WR
RD, CS, RST, TRITST
SDA, TXENA, UPDA, SCKLA, FSRA
SDB, TXENB, UPDB, SCKLB, FSRB
SDC, TXENC, UPDC, SCKLC, FSRC
SDD, TXEND, UPDD, SCKLD, FSRD
CLK
EXTERNAL CLK
U6 J11
OSC SMA
U7
CY7B9111V
CLOCK BUF.
TO DEVICE CLKS
mmabl
e
Upcon
J8-CONTROL
J17-FPGA DEBUG
IOUT<19:0> QOUT<19:0>
J14
SMA
QOUT
verter,
Digital
Up
U12
REG
3.3V
2.5V
5.0V
U8
DS90CR217
LVDS
U9
DS90CR217
LVDS
CAS-SYNCO
CAS-OUT-CLK
U11
HI5828
DAC
J15
SMA
IOUT
Conver
ter,
Interpo
U13
REG
J16
V IN
J12
IOUT
J13
QOUT
J3 IOUT<19:0>
J4 QOUT<19:0>
lation,
Baseba
nd to
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc.
Copyright ? Intersil Americas Inc. 2001, All Rights Reserved
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